Abstracts of invited talks
Peter Alfke (Xilinx)
Virtex-6 and Spartan-6, plus a Look into the Future
Recently, Xilinx introduced two new FPGA families, Virtex-6 and Spartan-6, closely related in architecture, but each optimized for different markets and applications:
Virtex-6 for high performance, features and capacity;
Spartan-6 for low cost and low power consumption.
Both families take advantage of 40/45 nm technology, and both are derived from the successful Virtex-5 architecture.
I will give an overview of the salient features and capabilities of both families.
Then I will give a peek into the future, explaining the impact of rapidly rising development costs for all future technology nodes. That limits ASICs and ASSPs to serve only high-volume opportunities, but offers unique advantages for FPGAs. But we need to overcome certain technical obstacles and streamline the user’s design process.
Shay Gueron (University of Haifa and Intel Corporation)
Intel's New AES and Carry-Less Multiplication Instructions - Applications and
Intel is adding to its processors 6 new instructions (AESENC,
AESENCLAST, AESDEC, AESDELAST, AESIMC, AESKEYGENASSIST) that facilitate secure
and high performance AES encryption, decryption, and key expansion, and one new
instructions (PCLMULQDQ) that performs carry-lee multiplication. PCLMULQDQ can
be used in several applications, including elliptic curve cryptography, CRC,
and the Galois Counter Mode (GCM). The talk will provide details on the
instructions, their various usage models, and how they enhance performance and
security. In particular, we will explain why and how parallel modes of
operation can gain significantly from the instructions.